`timescale 1ns / 10ps
module single_bit_test;

	reg a_in, b_in, c_in;
	wire s_out, c_out;

	integer i;

	single_bit_full_adder sbfa (.a(a_in), .b(b_in), .c(c_in), .s(s_out), .cout(c_out));

	initial begin

		$dumpfile("sbfa.vcd");
		$dumpvars(0, single_bit_test);
		
		{a_in, b_in, c_in} <= 0;

		for (i = 0; i < 8; i+=1) begin
			#10;
		 	$monitor("A=0x%0h B=0x%0h Cin=0x%h Sout=0x%h Cout=0x%h", a_in, b_in, c_in, s_out, c_out);
			{a_in, b_in, c_in} <= i;
		end
		#10 $monitor("DONE");

	end

endmodule
